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mosel vitelic 1 V436516S04VATG-75 3.3 volt 16m x 64 high performance pc133 unbuffered sdram module preliminary V436516S04VATG-75 rev. 2.0 july 2001 features 168 pin unbuffered 16,777,216 x 64 bit oganization sdram dimm utilizes high performance 128 mbit, 16m x 8 sdram in tsopii-54 packages fully pc board layout compatible to intel? rev 1.0 module specification single +3.3v (?0.3v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs, outputs are lvttl compatible 4096 refresh cycles every 64 ms serial present detect (spd) sdram performance supported latencies at 133 mhz operation description the V436516S04VATG-75 memory module is organized 16,777,216 x 64 bits in a 168 pin dual in line memory module (dimm). the 16m x 64 memory module uses 8 mosel-vitelic 16m x 8 sdram. the x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. component used -7 units t ck clock frequency (max.) cl=3 143 mhz cl=2 133 mhz t ac clock access time cas latency cl=3 5.4 ns cl=2 5.4 ns cl t rcd t rp t rc 3338clk 2228clk
2 mosel vitelic V436516S04VATG-75 V436516S04VATG-75 rev. 2.0 july 2001 pin configurations (front side/back side) notes: * these pins are not used in this module. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vss i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 i/o9 vss i/o10 i/o11 i/o12 i/o13 i/o14 vcc i/o15 i/o16 cbo* cb1* vss nc nc vcc we dqm0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 dqm1 cs0 du vss a0 a2 a4 a6 a8 a10(ap) ba1 vcc vcc clk0 vss du cs2 dqm2 dqm3 du vcc nc nc cb2* cb3* vss i/o17 i/o18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 i/o19 i/o20 vcc i/o21 nc du cke1 vss i/o22 i/o23 i/o24 vss i/o25 i/o26 i/o27 i/o28 vcc i/o29 i/o30 i/o31 i/o32 vss clk2 nc wp sda scl vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 vss i/o33 i/o34 i/o35 i/o36 vcc i/o37 i/o38 i/o39 i/o40 i/o41 vss i/o42 i/o43 i/o44 i/o45 i/o46 vcc i/o47 i/o48 cb4* cb5* vss nc nc vcc cas dqm4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 dqm5 cs1 ras vss a1 a3 a5 a7 a9 ba0 a11 vcc clk1 nc vss cke0 cs3 dqm6 dqm7 du vcc nc nc cb6* cb7* vss i/o49 i/o50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 i/o51 i/o52 vcc i/o53 nc du nc vss i/o54 i/o55 i/o56 vss i/o57 i/o58 i/o59 i/o60 vcc i/o61 i/o62 i/o63 i/o64 vss clk3 nc sa0 sa1 sa2 vcc pin names a0?11 address inputs i/o1?/o64 data inputs/outputs ras row address strobe cas column address strobe we read/write input ba0, ba1 bank selects cke0 , cke1 clock enable cs 0 ?s 3 chip select clk0?lk3 clock input dqm0?qm7 data mask vcc power (+3.3 volts) vss ground scl clock for presence detect sda serial data out for presence detect sa0?2 serial data in for presence detect cb0?b7 check bits (x72 organization) nc no connection du don? use
mosel vitelic V436516S04VATG-75 3 V436516S04VATG-75 rev. 2.0 july 2001 part number information block diagram sdram 3.3v v436516s04vtg-75-02 4 mosel-vitelic manufactured v 168 pin unbuffered dimm x 8 component s refresh rate 4k 0 3 depth 16 4 banks 4 tsop width 65 lvttl v gold g - 133 mhz (pc133 3-3-3) (pc133 2-2-2) 75 t dqm0 i/o1 i/o8 cs0 10 10 10 10 we we dqm4 i/o40 i/o33 dqm1 i/o9 i/o16 dqm5 i/o48 i/o41 dqm2 i/o17 i/o24 cs2 10 10 10 10 dqm6 i/o49 i/o56 dqm3 i/o25 i/o32 dqm7 i/o57 i/o64 v436516s04vtg-75-03 we: sdram d0-d7 cke: sdram d0-d7 ras: sdram d0-d7 a(11:0): sdram d0-d7 ba0, ba1: sdram d0-d7 cke0 ras cas we a(11:0) ba0, ba1 cas: sdram d0-d7 c0-c15 d0-d7 d0-d7 v cc v ss scl0 sa2 sa1 sa0 sda wp e 2 prom spd (256 word x 8 bits) 47k clock wiring clock input load clk0 4 sdrams +3.3pf cap clk1 termination clk2 4 sdrams +3.3pf cap clk3 termination d4 dqm i/o1 i/o8 cs d5 dqm i/o1 i/o8 cs d6 dqm i/o1 i/o8 cs d7 dqm i/o1 i/o8 cs dqm i/o1 i/o8 cs d0 dqm i/o1 i/o8 cs d1 dqm i/o1 i/o8 cs d2 dqm i/o1 i/o8 cs d3 we we we we we we we
4 mosel vitelic V436516S04VATG-75 V436516S04VATG-75 rev. 2.0 july 2001 serial presence detect information a serial presence detect storage device - e 2 prom - is assembled onto the module. informa- tion about the module configuration, speed, etc. is written into the e 2 prom device during module pro- duction using a serial presence detect protocol (i 2 c synchronous 2-wire bus) spd-table for pc133 modules: byte number function described spd entry value hex value 16mx64 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addresses (for x8 sdram) 10 0a 5 number of dimm banks 1 01 6 module data width 64 40 7 module data width (continued) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 s80 13 sdram width, primary x8 08 14 error checking sdram data width n/a / x8 00 15 minimum clock delay from back to back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cl = 3 04 19 cs latencies cs latency = 0 01 20 we latencies wl = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general vcc tol 10% 0e 23 minimum clock cycle time at cas latency = 2 not supported 00 24 maximum data access time from clock for cl = 2 not supported 00 25 minimum clock cycle time at cl = 1 not supported 00 26 maximum data access time from clock at cl = 1 not supported 00 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay t rrd 15 ns 0f 29 minimum ras to cas delay t rcd 20 ns 14 30 minimum ras pulse width t ras 45 ns 2d
mosel vitelic V436516S04VATG-75 5 V436516S04VATG-75 rev. 2.0 july 2001 dc characteristics t a = 0 c to 70 c; v ss = 0 v; v dd , v ddq = 3.3v 0.3v 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08 62-61 superset information (may be used in future) 00 62 spd revision revision 2.0 02 63 checksum for bytes 0 - 62 1d 64 manufacturer s jedec id code mosel vitelic 40 65-71 manufacturer s jedec id code (cont.) 00 72 manufacturing location 73-90 module part number (ascii) V436516S04VATG-75 91-92 pcb identification code 93 assembly manufacturing date (year) 94 assembly manufacturing date (week) 95-98 assembly serial number 99-125 reserved 00 126 intel specification for frequency 64 127 reserved ad 128+ unused storage location 00 symbol parameter limit values unit min. max. v ih input high voltage 2.0 v cc +0.3 v v il input low voltage 0.5 0.8 v v oh output high voltage (i out = 2.0 ma) 2.4 v v ol output low voltage (i out = 2.0 ma) 0.4 v i i(l) input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0v) 40 40 a i o(l) output leakage current (dq is disabled, 0v < v out < v cc ) 40 40 a spd-table for pc133 modules: (continued) byte number function described spd entry value hex value 16mx64
6 mosel vitelic V436516S04VATG-75 V436516S04VATG-75 rev. 2.0 july 2001 capacitance t a = 0 c to 70 c; v dd = 3.3v 0.3v, f = 1 mhz absolute maximum ratings symbol parameter limit values unit max. 16m x 64 c i1 input capacitance (a0 to a11, ras , cas , we )60pf c i2 input capacitance (cs0 -cs3 )30pf c icl input capacitance (clk0-clk3) 22 pf c i3 input capacitance (cke0, cke1) 50 pf c i4 input capacitance (dqm0-dqm7) 15 pf c io input/output capacitance (i/o1-i/064) 15 pf c sc input capacitance (scl, sa0-2) 8 pf c sd input/output capacitance (sa0-sa2) 10 pf parameter max. units voltage on vdd supply relative to v ss -1 to 4.6 v voltage on input relative to v ss -1 to 4.6 v operating temperature 0 to +70 c storage temperature -55 to 125 c power dissipation 6w operating currents t a = 0 c to 70 c, v cc = 3.3v 0.3v (recommended operating conditions otherwise noted) symbol parameter & test condition max. unit note -75 icc1 operating current t rc = t rcmin. , t rc = t ckmin . active-precharge command cycling, without burst operation 1 bank operation 1040 ma 7 icc2p precharge standby current in power down mode cs =v ih , cke v il(max) t ck = min. 16 ma 7 icc2ps t ck = infinity 8 ma 7 icc2n precharge standby current in non-power down mode cs =v ih , cke v il(max) t ck = min. 400 ma icc2ns t ck = infinity 40 ma icc3 no operating current t ck = min, cs = v ih(min) bank ; active state ( 4 banks) cke v ih(min.) 540 ma icc3p cke v il(max.) (power down mode) 64 ma
mosel vitelic V436516S04VATG-75 7 V436516S04VATG-75 rev. 2.0 july 2001 notes: 1. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 2. these parameter depend on output loading. specified values are obtained with output open. icc4 burst operating current t ck = min read/write command cycling 1120 ma 7,8 icc5 auto refresh current t ck = min auto refresh command cycling 1680 ma 7 icc6 self refresh current self refresh mode, cke=0.2v 16 ma l-version 8 ma ac characteristics t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns # symbol parameter limit values unit note -75 min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 7.5 10 s ns ns 2t ck clock frequency cas latency = 3 cas latency = 2 133 100 mhz mhz 3t ac access time from clock cas latency = 3 cas latency = 2 _ 5.4 6 ns ns 2, 4 4t ch clock high pulse width 2.5 ns 5t cl clock low pulse width 2.5 ns 6t t transition tim 0.3 1.2 ns setup and hold times 7t is input setup time 1.5 ns 5 8t ih input hold time 0.8 ns 5 9t cks input setup time 1.5 ns 5 10 t ckh cke hold time 0.8 ns 5 11 t rsc mode register set-up time 15 ns 12 t sb power down mode entry time 0 7.5 ns operating currents t a = 0 c to 70 c, v cc = 3.3v 0.3v (recommended operating conditions otherwise noted) (continued) symbol parameter & test condition max. unit note -75
8 mosel vitelic V436516S04VATG-75 V436516S04VATG-75 rev. 2.0 july 2001 common parameters 13 t rcd row to column delay time 20 ns 6 14 t rp row precharge time 20 ns 6 15 t ras row active time 45 100k ns 6 16 t rc row cycle time 60 ns 6 17 t rrd activate(a) to activate(b) command period 15 ns 6 18 t ccd cas (a) to cas (b) command period 1 clk refresh cycle 19 t ref refresh period (4096 cycles) 64 ms 20 t srex self refresh exit time 10 ns read cycle 21 t oh data out hold time 2.7 ns 2 22 t lz data out to low impedance time 1 ns 23 t hz data out to high impedance time 5.4 ns 7 24 t dqz dqm data out disable latency 2 clk write cycle 25 t wr write recovery time 1 clk 26 t dqw dqm write mask latency 0 clk ac characteristics t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns (continued) # symbol parameter limit values unit note -75 min. max.
mosel vitelic V436516S04VATG-75 9 V436516S04VATG-75 rev. 2.0 july 2001 notes: 1. the specified values are valid when addresses are changed no more than once during t ck (min.) and when no operation commands are registered on every rising clock edge during t rc (min). values are shown per module bank. 2. the specified values are valid when data inputs (dq s) are stable during t rc (min.). 3. all ac characteristics are shown for device level. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0v. 5. if clock rising time is longer than 1 ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5v 7. if t t is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 10. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t dal is equivalent to t dpl + t rp . 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t tcl tch i/o measurement conditions for tac and toh 50 pf
10 mosel vitelic V436516S04VATG-75 V436516S04VATG-75 rev. 2.0 july 2001 package diagram sdram dimm module package v436516s04vtg-75-04 127.35 133.35 42.18 d 66.68 3.0 35.00 17.78 11011 4041 84 85 94 95 124 125 168 b a 6.35 2.26 radius 1.27 + 0.10 detail a 3.125 8.25 4.45 2.0 c 6.35 detail b 3.125 2.0 1.0 + 0.5 1.27 detail c 2.4 min. 0.2 0.15 tolerances: (0.13) unless otherwise specified. (2.54 max) all measurements in mm 1.27 0.100
mosel vitelic V436516S04VATG-75 11 V436516S04VATG-75 rev. 2.0 july 2001 label information c l = 3 (clk) t rcd = 3 (clk) t rp = 3 (clk) t ac = 5.4 ns 333 u unbuffered dimm pc133 54 jedec spd revision 2.0 2 v436516s04vtg-75 pc133u-333-542-a taiwan xxxx-xxxxxxx a gerber file intel pc100 x 8 based -- - mosel vitelic part number dimm manufacture date code trace code criteria of pc100 or pc133 (refer to mvi datasheet)
mosel vitelic worldwide offices V436516S04VATG-75 ? copyright 2001, mosel vitelic inc. 7/01 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-826-6176 fax: 214-828-9754

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